In recent years, in the area of semiconductor memory devices such as DRAM, 4M and 16M DRAMs have been mass-produced, and 64M DRAMs have been studied. In DRAMs, the typical three dimensional structures such as a trench type and a stack type have been developed. The trench type is manufactured in a groove provided on the semiconductor substrate, and the stack type is formed by laminating in three dimensions the conductive layers on the surface of the semiconductor substrate. The trench type has a flatter surface than the stack type, providing advantages for lithography but has serious operating disadvantages. The operation voltage is changed by leakage of current and punch-through between adjacent trenches. Electron-hole pairs generated by .alpha.-particles transmitted inside the substrate are also a problem.
The stack type is formed by laminating element layers on the substrate, and the fabrication process sequence is simpler than for the trench type and does not have the operating deficits noted above. As a result, the stack type is more attractive than the trench type.
A limiting factor in the construction of stack type DRAMs in smaller cell sizes is the minimum storage capacity of 25 fF required for proper operation of a DRAM, that is, the cell capacity required per cell and the practical limit of photolithography techniques for achieving smaller dimensions. As the memory device is made to be more highly integrated and thus smaller in size, the area occupied by each cell is reduced, thus reducing the area available for each capacitor. To be functionally operable, the capacitor must have a large capacity, even as the size of the memory cell is reduced.
The chip size of a DRAM product is determined by the formula: EQU Chip Area=AP+AM
Where:
AP is the Area of Peripheral circuits; and PA1 AM is the Area of total Memory cells and is calculated by the formula: EQU AM=Total Bits (or density).times.a Cell Area PA1 .delta.=Spacing of a bit line contact to the word line due to alignment limitations of photolithography (alignment errors); PA1 WP=Word Line Pitch; and PA1 AE=Area Efficiency. PA1 a) depositing a form material on the surface of a product material; PA1 b) removing a portion of the form material by vertical etching using photolithography to leave a sidewall of said form material; PA1 c) depositing a layer of masking material over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material; PA1 d) removing masking material by vertical RIE until the form material is exposed, leaving a predetermined width of masking material, and removing the form material until the underlying product material is exposed; PA1 e) removing portions of the product material which are not protected by the masking material to leave a desired width of product material corresponding to the width of the masking material; and PA1 f) removing the masking material, leaving a desired width of said product material. PA1 a) depositing a form material on the surface of a product material; PA1 b) removing a center portion of the form material by vertical etching using photolithography to leave form materials having widths W with opposed sidewalls spaced apart by a distance D which is greater than the desired spacing d by 2.DELTA.; PA1 c) depositing a layer of masking material over the form material and product material, the layer of masking material having a thickness correlating to .DELTA.; PA1 d) removing masking material by vertical RIE until the form material is exposed, leaving .DELTA. widths of masking material contacting each of the opposed sidewalls of the form material; PA1 e) removing form material by etching; PA1 e) removing portions of the product material which are not protected by the masking material; and PA1 f) removing the form material and the masking material, leaving adjacent pairs of adjacent widths of product material, each having a width e of in a range down to 800 .ANG., the desired spacing d between adjacent pairs of product material being in a range down to 700 .ANG.; and a spacing W between adjacent widths of a product material. PA1 a) depositing a form material on the surface of a product material; PA1 b) forming an array of photolithographic masking materials spaced apart by a distance D; PA1 c) removing portions of the form material by vertical etching to leave an array of form materials with opposed sidewalls spaced apart by a distance D which is greater than spacing d by 2.DELTA. and removing the photolithographic masking materials; PA1 c) depositing a layer of second masking material over the form material and product material, the layer of second masking material having a thickness correlating to .DELTA.; PA1 d) removing second masking material by vertical RIE until the form material is exposed, leaving .DELTA. widths of opposed second masking material contacting each of the opposed sidewalls of the form material, the distance between the opposed widths of second masking material being in a range in a range down to 700 .ANG.. PA1 oxidizing the exposed surfaces to effect oxidation of the polysilicon and the underlying substrate silicon; and PA1 removing the form material and polysilicon to leave a silicon substrate having field oxide portions with widths in a range down to 1000 .ANG.. PA1 a) depositing a conductive layer in electrical contact with an active capacitor contact area of a substrate; PA1 b) depositing a upper layer of nitride, oxide or combination thereof on the surface of the conductive layer; PA1 c) forming a mask on the surface of the upper layer, the outer boundary of the mask positioned to define the inner walls of the capacitor; PA1 d) removing the upper layer and optional portions of the conductive layer by RIE to a depth which correlates to the sidewall thickness of the capacitor and removing the mask; PA1 e) depositing a layer of oxide material on the surface obtained in step (d); PA1 f) removing oxide by RIE until oxide is removed from the upper layer, leaving a shoulder of mask oxide on the surface of the upper layer and the conductive layer; PA1 g) removing the upper layer by etching and removing portions of the conductive layer which are not covered by the shoulder of mask oxide by RIE, leaving the sidewalls and floor of the capacitor; PA1 h) removing mask oxide by etching to leave a cup-shaped capacitor plate; PA1 i) depositing a layer of dielectric on the surface of the capacitor plate; and PA1 j) forming a conductive layer on the layer of dielectric to form a capacitor. PA1 a) depositing a layer of gate material on a layer of gate oxide supported by active silicon substrate; PA1 b) depositing an upper layer comprising nitride or oxide or combinations thereof on the gate material; PA1 c) forming an array of photolithography masked areas defining spaces between adjacent transistor gates on the upper layer, the distances between adjacent masked areas is D; PA1 d) removing the upper layer not covered by the masking areas by RIE and removing the photoresist; PA1 e) depositing mask oxide on the upper surface obtained in step (d); PA1 f) removing mask oxide by RIE, leaving shoulders of oxide mask adjacent the upper layer having a thickness .DELTA.; PA1 g) removing upper layer by etching and removing gate material by RIE to leave an array of mask oxide protected gates; PA1 h) removing mask oxide by etching, leaving an array of gates with width e. PA1 i) a layer of masking oxide is deposited on the product of step (h); PA1 j) masking oxide is removed by RIE to leave shoulders of mask oxide adjacent the gates and exposed areas of active substrate between the shoulders; and PA1 k) exposed areas of active substrate are doped by ion implantation. PA1 a) depositing successive pad oxide, polysilicon and upper nitride layers on a silicon substrate; PA1 b) forming resist mask portions on the nitride layer by photolithography to define the field oxide area and portions of the nitride to remain and removing the areas of nitride and a partial polysilicon unprotected by the mask portions by RIE, and removing the resist mask portions; PA1 c) depositing a masking layer of polysilicon on the upper surfaces of the product of step (b); PA1 d) removing the masking polysilicon by RIE to leave shoulders of mask polysilicon and exposed areas of nitride between the shoulders; PA1 e) exposing the product of step (d) to oxidation to grow field oxide in the exposed areas of pad oxide.
Normally, AM occupies more than 55 percent of the total chip area in a high density DRAM. Because the smaller the chip size, the lower the production cost, every effort is directed to reducing the cell size. It can be shown that the memory cell size can be estimated by the formula: ##EQU1## Wherein: AP=Active Pitch;
In the produce and process of this invention, AE can be greater than previously known configurations, being above 80% and as high as about 100%.
Prior art approaches have focused on reducing the Cell Area by scaling but have reached limits in size reduction and tolerances due to the limits of photolithography, process techniques, and the need to make a capacitors having capacities greater than 25 fF. Similar constraints have limited the Area Efficiency for a typical 16M DRAM to less than 80 percent.